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» Reducing Compilation Time Overhead in Compiled Simulators
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ICCD
1999
IEEE
115views Hardware» more  ICCD 1999»
14 years 8 days ago
Customization of a CISC Processor Core for Low-Power Applications
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...
You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong...
SAC
2003
ACM
14 years 1 months ago
Real-Time Monitoring of Large Scientific Simulations
We present a distributed framework that enables real-time streaming and visualization of data generated by large remote simulations. We address issues arising from distributed cli...
Valerio Pascucci, Daniel E. Laney, Ray J. Frank, F...
USENIX
2000
13 years 9 months ago
FiST: A Language for Stackable File Systems
Traditional file system development is difficult. Stackable file systems promise to ease the development of file systems by offering a mechanism for incremental development. Unfor...
Erez Zadok, Jason Nieh
EWSN
2010
Springer
14 years 1 months ago
Wiselib: A Generic Algorithm Library for Heterogeneous Sensor Networks
One unfortunate consequence of the success story of wireless sensor networks (WSNs) in separate research communities is an evergrowing gap between theory and practice. Even though ...
Tobias Baumgartner, Ioannis Chatzigiannakis, S&aac...
CODES
2006
IEEE
14 years 2 months ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu