Sciweavers

663 search results - page 82 / 133
» Reducing Compilation Time Overhead in Compiled Simulators
Sort
View
WSC
2004
13 years 9 months ago
Permuted Weighted Area Estimators
Calvin and Nakayama previously introduced permuting as a way of improving existing standardized time series methods. The basic idea is to split a simulated sample path into nonove...
James M. Calvin, Marvin K. Nakayama
OOPSLA
2004
Springer
14 years 1 months ago
The garbage collection advantage: improving program locality
As improvements in processor speed continue to outpace improvements in cache and memory speed, poor locality increasingly degrades performance. Because copying garbage collectors ...
Xianglong Huang, Stephen M. Blackburn, Kathryn S. ...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
14 years 13 days ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
HPCA
1996
IEEE
14 years 6 days ago
A Comparison of Entry Consistency and Lazy Release Consistency Implementations
This paper compares several implementations of entry consistency (EC) and lazy release consistency (LRC), two relaxed memory models in use with software distributed shared memory ...
Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ra...
ITNG
2008
IEEE
14 years 2 months ago
Parallel FFT Algorithms on Network-on-Chips
This paper presents several parallel FFT algorithms with different degree of communication overhead for multiprocessors in Network-on-Chip(NoC) environment. Three different method...
Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh