663 search results - page 84 / 133 » Reducing Compilation Time Overhead in Compiled Simulators |
ACSAC
2007
IEEE
14 years 2 months ago
2007
IEEE
We have implemented an information flow framework for the Java Virtual Machine that combines static and dynamic techniques to capture not only explicit flows, but also implicit ...
CGO
2003
IEEE
14 years 1 months ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
IEEEPACT
1998
IEEE
14 years 9 days ago
1998
IEEE
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
PLDI
2005
ACM
14 years 1 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
This paper introduces a new abstraction to accelerate the readbarriers and write-barriers used by language runtime systems. We exploit the fact that, dynamically, many barrier exe...