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» Reducing Expression Size Using Rule-Based Integration
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GLVLSI
2005
IEEE
186views VLSI» more  GLVLSI 2005»
14 years 1 months ago
An FPGA design of AES encryption circuit with 128-bit keys
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. U...
Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
INFOCOM
1996
IEEE
13 years 11 months ago
Group Priority Scheduling
We present an end-to-end delay guarantee theorem for a class of guaranteed-deadline (GD) servers. The theorem can be instantiated to obtain end-to-end delay bounds for a variety of...
Simon S. Lam, Geoffrey G. Xie
AVI
2008
13 years 10 months ago
The in-context slider: a fluid interface component for visualization and adjustment of values while authoring
As information environments grow in complexity, we yearn for simple interfaces that streamline human cognition and effort. Users need to perform complex operations on thousands of...
Andrew Webb, Andruid Kerne
RECOMB
2002
Springer
14 years 8 months ago
String barcoding: uncovering optimal virus signatures
There are many critical situations when one needs to rapidly identify an unidentified pathogen from among a given set of previously sequenced pathogens. DNA or RNA hybridization c...
Sam Rash, Dan Gusfield
CSB
2003
IEEE
130views Bioinformatics» more  CSB 2003»
14 years 29 days ago
A Computational Approach to Reconstructing Gene Regulatory Networks
Reverse-engineering of gene networks using linear models often results in an underdetermined system because of excessive unknown parameters. In addition, the practical utility of ...
Xutao Deng, Hesham H. Ali