An FPGA design of AES encryption circuit with 128-bit keys

This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. Using the proposed architecture on the Altera Stratix EP1S20F780C5 FPGA, the AES-4SM achieves a throughput of 5.61 Gbps by using 20 M4Ks, and the AES-8SM achieves a throughput of 10.49 Gbps by using 40 M4Ks. Compared with the unrolling implementation that achieves a throughput of 20.48 Gbps by using 80 M4Ks on the same FPGA, implementations with the PPR architecture reduce the amount of memory up to 75% while increasing the memory efficiency (i.e., throughput divided by the size of memory for core) up to 9.6%. The PPR architecture fills the gap between unrolling and rolling architectures, and fits on less expensive FPGAs. Categories and Subject Descriptors: B.7.1 [INTEGRATED CIRCUITS]: Types and Design Styles – Algorithms implemented in hardware General Terms: Design, Experimentation

• Type: Conference
• Year: 2005
• Where: GLVLSI
• Authors: Hui Qin, Tsutomu Sasao, Yukihiro Iguchi
• Keywords: Gbps, GLVLSI 2005, PPR Architecture, Throughput, VLSI