339 search results - page 11 / 68 » Reducing Memory Ordering Overheads in Software Transactional... |
IISWC
2009
IEEE
14 years 3 months ago
2009
IEEE
— Programming to exploit the resources in a multicore system remains a major obstacle for both computer and software engineers. Transactional memory offers an attractive alternat...
CCS
2008
ACM
13 years 10 months ago
2008
ACM
Correct enforcement of authorization policies is a difficult task, especially for multi-threaded software. Even in carefully-reviewed code, unauthorized access may be possible in ...
FPGA
2012
ACM
12 years 4 months ago
2012
ACM
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
SPAA
2009
ACM
14 years 9 months ago
2009
ACM
This paper takes a step toward developing a theory for understanding aborts in transactional memory systems (TMs). Existing TMs may abort many transactions that could, in fact, co...
ASPLOS
2012
ACM
12 years 4 months ago
2012
ACM
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...