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HIPEAC
2007
Springer
14 years 2 months ago
Reducing Exit Stub Memory Consumption in Code Caches
Abstract. The interest in translation-based virtual execution environments (VEEs) is growing with the recognition of their importance in a variety of applications. However, due to ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 3 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman
ARC
2010
Springer
186views Hardware» more  ARC 2010»
13 years 12 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
ICCD
2007
IEEE
140views Hardware» more  ICCD 2007»
14 years 5 months ago
A low overhead hardware technique for software integrity and confidentiality
Software integrity and confidentiality play a central role in making embedded computer systems resilient to various malicious actions, such as software attacks; probing and tamper...
Austin Rogers, Milena Milenkovic, Aleksandar Milen...
IPPS
2009
IEEE
14 years 3 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...