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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
14 years 2 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
SPAA
2003
ACM
14 years 1 months ago
Nonblocking k-compare-single-swap
The current literature offers two extremes of nonblocking software synchronization support for concurrent data structure design: intricate designs of specific structures based o...
Victor Luchangco, Mark Moir, Nir Shavit
ASPLOS
2004
ACM
14 years 2 months ago
Devirtualizable virtual machines enabling general, single-node, online maintenance
Maintenance is the dominant source of downtime at high availability sites. Unfortunately, the dominant mechanism for reducing this downtime, cluster rolling upgrade, has two short...
David E. Lowell, Yasushi Saito, Eileen J. Samberg
CF
2011
ACM
12 years 8 months ago
SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors
Dynamic Information Flow Tracking (DIFT) is a powerful technique that can protect unmodified binaries from a broad range of vulnerabilities such as buffer overflow and code inj...
Meltem Ozsoy, Dmitry Ponomarev, Nael B. Abu-Ghazal...
CGO
2008
IEEE
14 years 3 months ago
Automatic array inlining in java virtual machines
Array inlining expands the concepts of object inlining to arrays. Groups of objects and arrays that reference each other are placed consecutively in memory so that their relative ...
Christian Wimmer, Hanspeter Mössenböck