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IPPS
1998
IEEE
13 years 12 months ago
Memory Hierarchy Management for Iterative Graph Structures
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
Ibraheem Al-Furaih, Sanjay Ranka
PODC
2005
ACM
14 years 1 months ago
Advanced contention management for dynamic software transactional memory
The obstruction-free Dynamic Software Transactional Memory (DSTM) system of Herlihy et al. allows only one transaction at a time to acquire an object for writing. Should a second ...
William N. Scherer III, Michael L. Scott
IFL
2004
Springer
131views Formal Methods» more  IFL 2004»
14 years 1 months ago
Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations
The message-passing paradigm is now widely accepted and used mainly for inter-process communication in distributed memory parallel systems. However, one of its disadvantages is the...
Alfredo Cristóbal-Salas, Andrey Chernykh, E...
IPPS
2006
IEEE
14 years 1 months ago
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
Yoshihiro Nakatani, Masanori Hariyama, Michitaka K...
PADS
2005
ACM
14 years 1 months ago
Performance Benchmark of a Parallel and Distributed Network Simulator
Simulation of large-scale networks requires enormous amounts of memory and processing time. One way of speeding up these simulations is to distribute the model over a number of co...
Samson Lee, John Leaney, Tim O'Neill, Mark Hunter