27 search results - page 4 / 6 » Reducing Memory and Traffic Requirements for Scalable Direct... |
ISCA
1994
IEEE
13 years 10 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
ASPLOS
2011
ACM
12 years 10 months ago
2011
ACM
The adoption of transactional memory is hindered by the high overhead of software transactional memory and the intrusive design changes required by previously proposed TM hardware...
SIGMETRICS
1996
ACM
13 years 10 months ago
1996
ACM
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
MICRO
2010
IEEE
13 years 4 months ago
2010
IEEE
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
MICRO
2010
IEEE
13 years 1 months ago
2010
IEEE
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...