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IPPS
2008
IEEE
14 years 2 months ago
A simple power-aware scheduling for multicore systems when running real-time applications
High-performance microprocessors, e.g., multithreaded and multicore processors, are being implemented in embedded real-time systems because of the increasing computational require...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
ICPP
2002
IEEE
14 years 17 days ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
VLSID
2004
IEEE
107views VLSI» more  VLSID 2004»
14 years 8 months ago
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
Sourabh Saluja, Anshul Kumar
IPPS
2005
IEEE
14 years 1 months ago
A Compiler-Enabled Model- and Measurement-Driven Adaptation Environment for Dependability and Performance
Traditional techniques for building dependable, highperformance distributed systems are too expensive for most non-critical systems, often causing dependability to be sidelined as...
Vikram S. Adve, Adnan Agbaria, Matti A. Hiltunen, ...
VECPAR
2004
Springer
14 years 29 days ago
Message Strip-Mining Heuristics for High Speed Networks
In this work we investigate how the compiler technique of message strip mining performs in practice on contemporary high performance networks. Message strip mining attempts to redu...
Costin Iancu, Parry Husbands, Wei Chen