293 search results - page 34 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
HPCA
2000
IEEE
14 years 2 days ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
PLDI
2012
ACM
11 years 10 months ago
2012
ACM
Automatic parallelization is a promising strategy to improve application performance in the multicore era. However, common programming practices such as the reuse of data structur...
IPPS
2003
IEEE
14 years 28 days ago
2003
IEEE
Fine-grained parallel applications require all their processes to run simultaneously on distinct processors to achieve good efficiency. This is typically accomplished by space sl...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...