When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register ...
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered...
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abe...
—Register allocation is an important component of every compiler and numerous studies have investigated ways to improve allocation quality or reduce allocation time. However, tec...