40 search results - page 6 / 8 » Reducing cache misses through programmable decoders |
SIGMOD
2001
ACM
14 years 7 months ago
2001
ACM
This paper proposes and evaluates Prefetching B+ -Trees pB+ -Trees, which use prefetching to accelerate two important operations on B+ -Tree indices: searches and range scans. To ...
SIGMETRICS
1993
ACM
13 years 11 months ago
1993
ACM
Recently there has been a surge of interest in developing performance debugging tools to help programmers tune their applications for better memory performance [2, 4, 10]. These t...
IPPS
2003
IEEE
14 years 24 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
EUROSYS
2006
ACM
13 years 11 months ago
2006
ACM
This paper presents a connection handoff interface between the operating system and the network interface. Using this interface, the operating system can offload a subset of TCP c...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Store misses cause significant delays in shared-memory multiprocessors because of limited store buffering and ordering constraints required for proper synchronization. Today, prog...