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ANCS
2009
ACM
13 years 5 months ago
Design of a scalable nanophotonic interconnect for future multicores
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
Avinash Karanth Kodi, Randy Morris
MOBICOM
2009
ACM
14 years 2 months ago
A scalable micro wireless interconnect structure for CMPs
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to inte...
Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, So...
HPCA
2011
IEEE
12 years 11 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
HOTI
2008
IEEE
14 years 1 months ago
High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections
In this paper, we propose an Ethernet-based transmission-guaranteed, congestion-controlled network using a simplified multi-path aggregation scheme. Multi-path aggregation increas...
Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Hig...
ICCAD
2005
IEEE
101views Hardware» more  ICCAD 2005»
14 years 4 months ago
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variat
In this paper we propose a novel parameterized interconnect order reduction algorithm, CORE, to efficiently capture both inter-die and intra-die variations. CORE applies a two-ste...
Xin Li, Peng Li, Lawrence T. Pileggi