605 search results - page 18 / 121 » Reducing complexity in tree-like computer interconnection ne... |
EUROPAR
2009
Springer
14 years 2 months ago
2009
Springer
Optimal network performance is critical to efficient parallel scaling for communication-bound applications on large machines. With wormhole routing, no-load latencies do not increa...
Publication
A large class of systems of biological and technological relevance can be described as analog networks, that is, collections of dynamic devices interconnected by links of varying s...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
NCA
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper deals with general nested loops and proposes a novel scheduling methodology for reducing the communication cost of parallel programs. General loops contain complex loop...
ISCA
2010
IEEE
14 years 18 days ago
2010
IEEE
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...