Sciweavers

605 search results - page 7 / 121
» Reducing complexity in tree-like computer interconnection ne...
Sort
View
AINA
2007
IEEE
14 years 1 months ago
Reducing the Complexity in the Distributed Multiplication Protocol of Two Polynomially Shared Values
The multiparty multiplication of two polynomially shared values over Zq with a public prime number q is an important module in distributed computations. The multiplication protoco...
Peter Lory
NCA
2006
IEEE
14 years 1 months ago
Full QoS Support with 2 VCs for Single-chip Switches
Current interconnection standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations ...
Alejandro Martínez, Francisco José A...
CLUSTER
2009
IEEE
14 years 2 months ago
Reducing network contention with mixed workloads on modern multicore, clusters
Abstract—Multi-core systems are now extremely common in modern clusters. In the past commodity systems may have had up to two or four CPUs per compute node. In modern clusters, t...
Matthew J. Koop, Miao Luo, Dhabaleswar K. Panda
DAC
2008
ACM
14 years 8 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin
ICPP
2000
IEEE
13 years 12 months ago
Multilayer VLSI Layout for Interconnection Networks
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz P...