64 search results - page 13 / 13 » Reducing dTLB Energy Through Dynamic Resizing |
ASPDAC
2005
ACM
14 years 1 months ago
2005
ACM
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
ICRA
2003
IEEE
14 years 27 days ago
2003
IEEE
- This paper presents a third-order spline interpolation based trajectory planning method which is aiming to achieve smooth biped swing leg trajectory by reducing the instant veloc...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
ICPPW
2007
IEEE
14 years 1 months ago
2007
IEEE
We study the role of task-level scheduling in power management on multicore multiple voltage embedded systems. Multicore on-achip, in particular DSP systems, can greatly improve p...