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» Reducing the Costs of Bounded-Exhaustive Testing
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ET
2002
84views more  ET 2002»
13 years 7 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 1 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
14 years 1 months ago
A dynamic test compaction procedure for high-quality path delay testing
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, T...
AAAI
2012
11 years 10 months ago
POMDPs Make Better Hackers: Accounting for Uncertainty in Penetration Testing
Penetration Testing is a methodology for assessing network security, by generating and executing possible hacking attacks. Doing so automatically allows for regular and systematic...
Carlos Sarraute, Olivier Buffet, Jörg Hoffman...
QSIC
2008
IEEE
14 years 1 months ago
Using Machine Learning to Refine Black-Box Test Specifications and Test Suites
In the context of open source development or software evolution, developers are often faced with test suites which have been developed with no apparent rationale and which may nee...
Lionel C. Briand, Yvan Labiche, Zaheer Bawar