Sciweavers

221 search results - page 5 / 45
» Reducing the Interconnection Network Cost of Chip Multiproce...
Sort
View
IJES
2008
128views more  IJES 2008»
13 years 8 months ago
On-chip implementation of multiprocessor networks and switch fabrics
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
Terry Tao Ye, Giovanni De Micheli
TPDS
2010
125views more  TPDS 2010»
13 years 3 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
14 years 1 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
HPCA
1995
IEEE
14 years 4 days ago
Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems
—Reducing communication latency, which is a performance bottleneck in optically interconnected multiprocessor systems, is of prominent importance. A conventional approach for est...
Chunming Qiao, Rami G. Melhem
HPCA
2009
IEEE
14 years 3 months ago
MRR: Enabling fully adaptive multicast routing for CMP interconnection networks
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
Pablo Abad Fidalgo, Valentin Puente, José-&...