723 search results - page 58 / 145 » Reducing the complexity of the issue logic |
ICNP
2009
IEEE
14 years 2 months ago
2009
IEEE
—Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significan...
ISQED
2011
IEEE
12 years 11 months ago
2011
IEEE
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
— To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scal...
CODES
2002
IEEE
14 years 19 days ago
2002
IEEE
This paper describes the formal verification of the recently introduced Dual Transition Petri Net (DTPN) models [12], using model checking techniques. The methodology presented a...
MEDINFO
2007
13 years 9 months ago
2007
After a critical review of the present architecture of SNOMED CT, addressing both logical and ontological issues, we present a roadmap towards an overall improvement of this termi...