201 search results - page 19 / 41 » Reducing the number of clock variables of timed automata |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
CSCLP
2005
Springer
14 years 1 months ago
2005
Springer
CSP search algorithms are exponential in the worst-case. A trivial upper bound on the time complexity of CSP search algorithms is O∗ (dn ), where n and d are the number of variab...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— In this paper, we study the problem of exact emulation of two types of optical queues: (i) N-to-1 output-buffered multiplexers with variable length bursts, and (ii) N Ã...
JSC
2007
13 years 7 months ago
2007
We present new deterministic and probabilistic algorithms that reduce the factorization of dense polynomials from several to one variable. The deterministic algorithm runs in sub-...