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» Reducing the number of clock variables of timed automata
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ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
12 years 11 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti
ASPDAC
2006
ACM
124views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Functional modeling techniques for efficient SW code generation of video codec applications
–Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
HPDC
2009
IEEE
14 years 2 months ago
Trace-based evaluation of job runtime and queue wait time predictions in grids
Large-scale distributed computing systems such as grids are serving a growing number of scientists. These environments bring about not only the advantages of an economy of scale, ...
Omer Ozan Sonmez, Nezih Yigitbasi, Alexandru Iosup...
AICOM
2004
92views more  AICOM 2004»
13 years 7 months ago
An efficient consistency algorithm for the Temporal Constraint Satisfaction Problem
Abstract. Dechter et al. [5] proposed solving the Temporal Constraint Satisfaction Problem (TCSP) by modeling it as a metaCSP, which is a finite CSP with a unique global constraint...
Berthe Y. Choueiry, Lin Xu
CAV
2009
Springer
215views Hardware» more  CAV 2009»
14 years 8 months ago
Homer: A Higher-Order Observational Equivalence Model checkER
We present HOMER, an observational-equivalence model checker for the 3rd-order fragment of Idealized Algol (IA) augmented with iteration. It works by first translating terms of the...
David Hopkins, C.-H. Luke Ong