201 search results - page 29 / 41 » Reducing the number of clock variables of timed automata |
IPCCC
2007
IEEE
14 years 1 months ago
2007
IEEE
Successes and failures during rescue operations after hurricane Katrina and the Twin Towers attack demonstrated the importance of supporting first responders with adequate means t...
CGO
2003
IEEE
14 years 26 days ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
JSA
2008
13 years 7 months ago
2008
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
ICC
2009
IEEE
14 years 2 months ago
2009
IEEE
—This paper presents the field-programmable gate array (FPGA) implementation of a variant of the LenstraLenstra-Lov´asz (LLL) lattice reduction (LR) algorithm, known as the Cla...
SEAL
1998
Springer
13 years 11 months ago
1998
Springer
Abstract. In this paper, we discuss an approach to an operator scheduling problem in a large organization over time with the aim of maintaining service quality and reducing total l...