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» Reducing the number of clock variables of timed automata
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FORMATS
2006
Springer
13 years 11 months ago
Adding Invariants to Event Zone Automata
Recently, a new approach to the symbolic model checking of timed automata based on a partial order semantics was introduced, which relies on event zones that use vectors of event o...
Peter Niebert, Hongyang Qu
CODES
2008
IEEE
14 years 2 months ago
System-level mitigation of WID leakage power variability using body-bias islands
Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ...
Siddharth Garg, Diana Marculescu
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
MOVEP
2000
136views Hardware» more  MOVEP 2000»
13 years 11 months ago
UPPAAL - Now, Next, and Future
Uppaal is a tool for modeling, simulation and verification of real-time systems, developed jointly by BRICS at Aalborg University and the Department of Computer Systems at Uppsala ...
Tobias Amnell, Gerd Behrmann, Johan Bengtsson, Ped...
MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
13 years 11 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...