The Multicluster Architecture: Reducing Cycle Time Through Partitioning

The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural registers. The motivation for the multicluster architecture is to reduce the clock cycle time, relative to a single-cluster architecture with the same number of hardware resources, by reducing the size and complexity of components on critical timing paths. Resource partitioning, however, introduces instruction-execution overhead and may reduce the number of concurrently executing instructions. To counter these two negative by-products of partitioning, we developed a static instruction scheduling algorithm. We describe this algorithm, and using tracedriven simulations of SPEC92 benchmarks, evaluate its effectiveness. This evaluation indicates that for the configurations considered, the multiclu...

• Type: Conference
• Year: 1997
• Where: MICRO
• Authors: Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
• Keywords: Clock Cycle Time, Dynamically-scheduled Architecture, Hardware, MICRO 1997, Multicluster Architecture