201 search results - page 9 / 41 » Reducing the number of clock variables of timed automata |
ACSD
2007
IEEE
13 years 9 months ago
2007
IEEE
We present an improvement of the SAT-based Unbounded Model Checking (UMC) algorithm. UMC, a symbolic approach introduced in [7], uses propositional formulas in conjunctive normal ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
The concept of improving the timing behavior of a circuit by relocating flip-flops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm propose...
FORMATS
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
EUROPAR
2001
Springer
14 years 1 days ago
2001
Springer
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
DSN
2005
IEEE
14 years 1 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...