65 search results - page 13 / 13 » Reducing traffic generated by conflict misses in caches |
JSA
2000
13 years 7 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
IEEEPACT
2003
IEEE
14 years 22 days ago
2003
IEEE
Modern architecture research relies heavily on detailed pipeline simulation. Simulating the full execution of an industry standard benchmark can take weeks to months to complete. ...
CASES
2010
ACM
13 years 5 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
IJHPCA
2010
13 years 6 months ago
2010
Sparse matrix operations achieve only small fractions of peak CPU speeds because of the use of specialized, indexbased matrix representations, which degrade cache utilization by i...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Runahead execution is a technique that improves processor performance by pre-executing the running application instead of stalling the processor when a long-latency cache miss occ...