65 search results - page 9 / 13 » Reducing traffic generated by conflict misses in caches |
SIGGRAPH
1999
ACM
13 years 11 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
ICS
2005
Tsinghua U.
14 years 29 days ago
2005
Tsinghua U.
As network traffic continues to increase and with the requirement to process packets at line rates, high performance routers need to forward millions of packets every second. Eve...
MTA
2006
13 years 7 months ago
2006
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...
HIPEAC
2011
Springer
12 years 7 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
EUROMICRO
1999
IEEE
13 years 11 months ago
1999
IEEE
This research proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are comp...