521 search results - page 35 / 105 » Reduction Strategies and Acyclicity |
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
SPAA
2003
ACM
14 years 1 months ago
2003
ACM
Recent research on processor microarchitecture suggests using instruction criticality as a metric to guide hardware control policies. Fields et al. [3, 4] have proposed a directed...
CP
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. Many real world problems, e.g. personnel scheduling and transportation planning, can be modeled naturally as Constrained Shortest Path Problems (CSPPs), i.e., as Shortest...
IEEEPACT
2002
IEEE
14 years 29 days ago
2002
IEEE
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
ICCAD
1997
IEEE
14 years 7 days ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...