73 search results - page 9 / 15 » Reduction of interpolants for logic synthesis |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
TCAD
2008
13 years 7 months ago
2008
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...