24 search results - page 4 / 5 » Reduction techniques for synchronous dataflow graphs |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
RSP
2000
IEEE
13 years 11 months ago
2000
IEEE
Dataflow programming has proven to be popular for representing applications in rapid prototyping tools for digital signal processing (DSP); however, existing dataflow design tools...
ASAP
2010
IEEE
13 years 9 months ago
2010
IEEE
Data-flow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of data-flow, termed synchronous data...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
VL
1995
IEEE
13 years 11 months ago
1995
IEEE
Buffering of intermediate results in dataflow diagrams can significantly reduce latency when a user browses these results or re-executes a diagram with slightly different inputs. ...