76 search results - page 11 / 16 » Redundancy in Instruction Sequences of Computer Programs |
PLDI
1999
ACM
13 years 11 months ago
1999
ACM
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper proposes a rapid and accurate evaluation scheme for cycle counts of a pipelined processor using evaluation reuse technique. Since exploration of an optimal processor is...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
LCTRTS
2009
Springer
14 years 2 months ago
2009
Springer
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...