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» Redundancy in Instruction Sequences of Computer Programs
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DAGSTUHL
2006
13 years 8 months ago
Program Compression
Abstract. The talk focused on a grammar-based technique for identifying redundancy in program code and taking advantage of that redundancy to reduce the memory required to store an...
William S. Evans
DSN
2006
IEEE
14 years 1 months ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August
HPCA
2000
IEEE
13 years 12 months ago
eXtended Block Cache
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing...
Stéphan Jourdan, Lihu Rappoport, Yoav Almog...
CGO
2005
IEEE
14 years 1 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
ALIFE
1999
13 years 7 months ago
An Approach to Biological Computation: Unicellular Core-Memory Creatures Evolved Using Genetic Algorithms
A novel machine language genetic programming system that uses one-dimensional core memories is proposed and simulated. The core is compared to a biochemical reaction space, and in ...
Hikeaki Suzuki