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» Redundancy in Instruction Sequences of Computer Programs
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ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
13 years 12 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
ASPLOS
2008
ACM
13 years 9 months ago
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
BMCBI
2008
211views more  BMCBI 2008»
13 years 7 months ago
CUDA compatible GPU cards as efficient hardware accelerators for Smith-Waterman sequence alignment
Background: Searching for similarities in protein and DNA databases has become a routine procedure in Molecular Biology. The Smith-Waterman algorithm has been available for more t...
Svetlin Manavski, Giorgio Valle
PLDI
1999
ACM
13 years 11 months ago
Load-Reuse Analysis: Design and Evaluation
Load-reuse analysis finds instructions that repeatedly access the same memory location. This location can be promoted to a register, eliminating redundant loads by reusing the re...
Rastislav Bodík, Rajiv Gupta, Mary Lou Soff...
BMCBI
2008
102views more  BMCBI 2008»
13 years 7 months ago
Ornithine decarboxylase antizyme finder (OAF): Fast and reliable detection of antizymes with frameshifts in mRNAs
Background: Ornithine decarboxylase antizymes are proteins which negatively regulate cellular polyamine levels via their affects on polyamine synthesis and cellular uptake. In vir...
Michaël Bekaert, Ivaylo P. Ivanov, John F. At...