Sciweavers

91 search results - page 15 / 19
» Register Allocation for Programs in SSA-Form
Sort
View
DAC
1997
ACM
13 years 11 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
LCPC
2000
Springer
13 years 11 months ago
Recursion Unrolling for Divide and Conquer Programs
This paper presents recursion unrolling, a technique for improving the performance of recursive computations. Conceptually, recursion unrolling inlines recursive calls to reduce c...
Radu Rugina, Martin C. Rinard
IEEEPACT
2009
IEEE
14 years 2 months ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
EGH
2005
Springer
14 years 1 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
LCTRTS
2009
Springer
14 years 2 months ago
Live-range unsplitting for faster optimal coalescing
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...
Sandrine Blazy, Benoît Robillard