1017 search results - page 126 / 204 » Register computations on ordinals |
PLDI
1999
ACM
14 years 4 days ago
1999
ACM
Load-reuse analysis finds instructions that repeatedly access the same memory location. This location can be promoted to a register, eliminating redundant loads by reusing the re...
FC
1997
Springer
13 years 12 months ago
1997
Springer
Abstract. SPEED is a private key block cipher. It supports three variable parameters: (1) data length — the length of a plaintext/ciphertext of SPEED can be 64, 128 or 256 bits. ...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
The last decade has witnessed the emergence of the Application Specific Instruction-set Processor (ASIP) as a viable platform for embedded systems. Extensible ASIPs allow the user...
GECCO
2008
Springer
13 years 9 months ago
2008
Springer
Based in part on observations about the incremental nature of most state changes in biological systems, we introduce the idea of Memory with Memory in Genetic Programming (GP), wh...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...