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IPPS
2006
IEEE
15 years 8 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
ISPASS
2006
IEEE
15 years 8 months ago
Comparing simulation techniques for microarchitecture-aware floorplanning
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
Vidyasagar Nookala, Ying Chen, David J. Lilja, Sac...
RTCSA
2005
IEEE
15 years 8 months ago
An On-Chip Garbage Collection Coprocessor for Embedded Real-Time Systems
Garbage collection considerably increases programmer productivity and software quality. However, it is difficult to implement garbage collection both efficiently and suitably fo...
Matthias Meyer
WWW
2005
ACM
15 years 8 months ago
Hera presentation generator
Semantic Web Information Systems (SWIS) are Web Information Systems that use Semantic Web technologies. Hera is a modeldriven design methodology for SWIS. In Hera, models are repr...
Flavius Frasincar, Geert-Jan Houben, Peter Barna
LCPC
2004
Springer
15 years 8 months ago
HiLO: High Level Optimization of FFTs
As computing platforms become more and more complex, the task of optimizing performance critical codes becomes more challenging. Recently, more attention has been focused on automa...
Nick Rizzolo, David A. Padua