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ANCS
2007
ACM
13 years 11 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
FCCM
2003
IEEE
185views VLSI» more  FCCM 2003»
14 years 22 days ago
Implementation of a Content-Scanning Module for an Internet Firewall
A module has been implemented in Field Programmable Gate Array (FPGA) hardware that scans the content of Internet packets at Gigabit/second rates. All of the packet processing ope...
James Moscola, John W. Lockwood, Ronald Prescott L...
FPL
2003
Springer
100views Hardware» more  FPL 2003»
14 years 19 days ago
An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall
An extensible firewall has been implemented that performs packet filtering, content scanning, and per-flow queuing of Internet packets at Gigabit/second rates. The firewall use...
John W. Lockwood, Christopher E. Neely, Christophe...