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» Reliability Analysis of Concurrent Systems Using LTSA
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DAC
2005
ACM
14 years 10 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
ASPLOS
2008
ACM
13 years 11 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
ICFEM
2003
Springer
14 years 2 months ago
Formalization, Testing and Execution of a Use Case Diagram
Abstract. Errors in a requirements model have prolonged detrimental effects on reliability, cost, and safety of a software system. It is very costly to fix these errors in later ...
Wuwei Shen, Shaoying Liu
TSE
2011
134views more  TSE 2011»
13 years 4 months ago
Verifying the Evolution of Probability Distributions Governed by a DTMC
— We propose a new probabilistic temporal logic iLTL which captures properties of systems whose state can be represented by probability mass functions (pmf’s). Using iLTL, we c...
YoungMin Kwon, Gul A. Agha
DAC
2006
ACM
14 years 10 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...