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FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
14 years 21 days ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
INTEGRATION
2000
71views more  INTEGRATION 2000»
13 years 7 months ago
A hardware implementation of realloc function
The memory intensive nature of object-oriented languages such as C++ and Java has created the need of a high-performance dynamic memory management. Objectoriented applications oft...
Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chan...
VLSISP
2010
148views more  VLSISP 2010»
13 years 5 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
ICASSP
2009
IEEE
14 years 2 months ago
Bandwidth adaptive hardware architecture of K-Means clustering for intelligent video processing
K-Means is a clustering algorithm that is widely applied in many elds, including pattern classi cation and multimedia analysis. Due to real-time requirements and computational-cos...
Tse-Wei Chen, Shao-Yi Chien
3DIM
2005
IEEE
14 years 1 months ago
3D Registration by Textured Spin-Images
This work is motivated by the desire of exploiting for 3D registration purposes the photometric information current range cameras typically associate to range data. Automatic pair...
Nicola Brusco, Marco Andreetto, Andrea Giorgi, Gui...