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» Remarks on Hardware Implementation of Image Processing Algor...
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ASPDAC
2000
ACM
92views Hardware» more  ASPDAC 2000»
14 years 1 months ago
Co-synthesis with custom ASICs
- This paper introduces the first hardwarekoftware co-synthesis algorithm that optimizes the implementations of ASICs that are used as processing elements for the embedded systems....
Yuan Xie, Wayne Wolf
ANCS
2008
ACM
13 years 11 months ago
Towards effective network algorithms on multi-core network processors
To build high-performance network devices with holistic security protection, a large number of algorithms have been proposed. However, multi-core implementation of the existing al...
Yaxuan Qi, Zongwei Zhou, Baohua Yang, Fei He, Yibo...
ICPR
2004
IEEE
14 years 10 months ago
BTF Image Space Utmost Compression and Modelling Method
The bidirectional texture function (BTF) describes texture appearance variations due to varying illumination and viewing conditions. This function is acquired by large number of m...
Jirí Filip, Michael Arnold, Michal Haindl
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
14 years 3 months ago
Image sensor with focal plane change event driven video compression
— An image sensor with focal plane based hardware acceleration of video compression is presented. The 90×90 pixel CMOS image sensor provides in-pixel processing of intensity cha...
Yu M. Chi, Ralph Etienne-Cummings, Gert Cauwenberg...
ICIP
2004
IEEE
14 years 10 months ago
Shear-resize factorizations for fast multi-modal volume registration
Intensity-based methods work well for multi-modal image registration owing to their effectiveness and simplicity, but the computation for geometric transforms is a heavy load. To ...
Ying Chen, Pengwei Hao, Jian Yu