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» Representational Reasoning and Verification
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ETFA
2006
IEEE
14 years 2 months ago
Modelling and Verification of IEC 61499 Applications using Prolog
This paper presents a new approach to modelling and verification of function block applications of the IEC 61499 standard. The approach uses the language of logic programming Prol...
Victor Dubinin, Valeriy Vyatkin, Hans-Michael Hani...
FMCAD
2008
Springer
13 years 10 months ago
Scaling Up the Formal Verification of Lustre Programs with SMT-Based Techniques
We present a general approach for verifying safety properties of Lustre programs automatically. Key aspects of the approach are the choice of an expressive first-order logic in wh...
George Hagen, Cesare Tinelli
ICFP
2004
ACM
14 years 8 months ago
Verification of safety properties for concurrent assembly code
Concurrency, as a useful feature of many modern programming languages and systems, is generally hard to reason about. Although existing work has explored the verification of concu...
Dachuan Yu, Zhong Shao
IAW
2003
IEEE
14 years 2 months ago
Static Verification of Worm and virus Behavior in binary Executables using Model Checking
- Use offormal methods in any application scenario requires a precise characterization and representation of the properties that need to be verified The target, which is desired ri...
Prabhat K. Singh, Arun Lakhotia
AAAI
2006
13 years 10 months ago
Constraint-Based Random Stimuli Generation for Hardware Verification
We report on random stimuli generation for hardware verification in IBM as a major application of various artificial intelligence technologies, including knowledge representation,...
Yehuda Naveh, Michal Rimon, Itai Jaeger, Yoav Katz...