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ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 11 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 11 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
MICRO
2009
IEEE
191views Hardware» more  MICRO 2009»
15 years 11 months ago
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches
Cache blocks often exhibit a small number of uses during their life time in the last-level cache. Past research has exploited this property in two different ways. First, replacem...
Mainak Chaudhuri
BTW
2009
Springer
114views Database» more  BTW 2009»
15 years 11 months ago
Value Demonstration of Embedded Analytics for Front Office Applications
: Users of front office applications such as call center or customer support applications make millions and millions of decisions each day without analytical support. For example, ...
Erik Nijkamp, Martin Oberhofer, Albert Maier
141
Voted
EUROSSC
2009
Springer
15 years 11 months ago
Time-Lag as Limiting Factor for Indoor Walking Navigation
Several navigation situations can be imagined where visual cueing is not practical or unfeasible, and where the hands are required exclusively for a certain task. The utilization o...
Andreas Riener, Markus Straub, Alois Ferscha
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