This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
Plug-in hybrid electric vehicles are expected to place a considerable strain on local electricity distribution networks, requiring charging to be coordinated in order to accommoda...
Enrico H. Gerding, Valentin Robu, Sebastian Stein,...
Product Line Architecture (PLA) plays a central role in software product line development. In order to support architecture-level variability modeling, most architecture descriptio...
Jiayi Zhu, Xin Peng, Stan Jarzabek, Zhenchang Xing...
Dense deployments of WLANs suffer from increased interference and as a result, reduced capacity. There are three main functions used to improve the overall network capacity: a) in...
Ioannis Broustis, Konstantina Papagiannaki, Srikan...