70 search results - page 8 / 14 » Retargetable Cache Simulation Using High Level Processor Mod... |
DSD
2008
IEEE
14 years 2 months ago
2008
IEEE
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
IEEEPACT
2003
IEEE
14 years 29 days ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
ISCA
1994
IEEE
13 years 11 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
ISPASS
2009
IEEE
14 years 2 months ago
2009
IEEE
Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manyco...