2778 search results - page 4 / 556 » Reuse Technique in Hardware Design |
HPCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
MSE
2003
IEEE
14 years 18 days ago
2003
IEEE
Intellectual property (IP) reuse based system design is becoming an industry standard recently. However, current educational system is not effective in the training of engineers ...
SBACPAD
2003
IEEE
14 years 18 days ago
2003
IEEE
Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ...
ASPDAC
2011
ACM
12 years 11 months ago
2011
ACM
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequent...