2778 search results - page 516 / 556 » Reuse Technique in Hardware Design |
IPPS
2000
IEEE
14 years 25 days ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
IPPS
2000
IEEE
14 years 25 days ago
2000
IEEE
Parallel simulation techniques are often employed to meet the computational requirements of large hardware simulations in order to reduce simulation time. In addition, partitionin...
HPCA
1999
IEEE
14 years 23 days ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
IEEEPACT
1999
IEEE
14 years 22 days ago
1999
IEEE
This paper presents the Cameron Project 1 , which aims to provide a high level, algorithmic language and optimizing compiler for the development of image processing applications o...
HPCA
1998
IEEE
14 years 21 days ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...