Sciweavers

2778 search results - page 554 / 556
» Reuse Technique in Hardware Design
Sort
View
APCSAC
2001
IEEE
13 years 10 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
USENIX
2008
13 years 9 months ago
A Multi-Site Virtual Cluster System for Wide Area Networks
A virtual cluster is a promising technology for reducing management costs and improving capacity utilization in datacenters and computer centers. However, recent cluster virtualiz...
Takahiro Hirofuchi, Takeshi Yokoi, Tadashi Ebara, ...
CODES
2006
IEEE
13 years 8 months ago
Architectural support for safe software execution on embedded processors
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
ECAI
2010
Springer
13 years 7 months ago
Parallel TBox Classification in Description Logics - First Experimental Results
Abstract. One of the most frequently used inference services of description logic reasoners classifies all named classes of OWL ontologies into a subsumption hierarchy. Due to emer...
Mina Aslani, Volker Haarslev
BMCBI
2008
115views more  BMCBI 2008»
13 years 6 months ago
BioGraphE: high-performance bionetwork analysis using the Biological Graph Environment
Background: Graphs and networks are common analysis representations for biological systems. Many traditional graph algorithms such as k-clique, k-coloring, and subgraph matching h...
George Chin Jr., Daniel G. Chavarría-Mirand...