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ISCA
2003
IEEE
120views Hardware» more  ISCA 2003»
14 years 3 months ago
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes
While removing software bugs consumes vast amounts of human time, hardware support for debugging in modern computers remains rudimentary. Fortunately, we show that mechanisms for ...
Milos Prvulovic, Josep Torrellas
ESOP
2000
Springer
14 years 1 months ago
Alias Types
Abstract. Linear type systems allow destructive operations such as object deallocation and imperative updates of functional data structures. These operations and others, such as th...
Frederick Smith, David Walker, J. Gregory Morriset...
DAGSTUHL
2008
13 years 11 months ago
Mathematica Connectivity to Interval Libraries filib++ and C-XSC
Abstract. Building interval software interoperability can be a good solution when re-using high-quality legacy code or when accessing functionalities unavailable natively in one of...
Evgenija D. Popova
ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
14 years 1 months ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
ICECCS
1998
IEEE
123views Hardware» more  ICECCS 1998»
14 years 2 months ago
Applying Slicing Technique to Software Architectures
Software architecture is receiving increasingly attention as a critical design level for software systems. As software architecture design resources (in the form of architectural ...
Jianjun Zhao